What is Pipeline HAZARDS ?

PIPELINE HAZARDS:

  Most of a pipeline hazard happens when the pipeline, or some 

portion of the pipeline,

  must stall because conditions do not permit continued 

execution. Such a pipeline

 The term "stall" also refers to a "pipeline bubble.". There are 

three types of hazards:

  resource, data, and control

RESOURCE HAZARDS:

  A resource hazard occurs when two (or 

more) instructions that are already in the pipeline 

need the same resource. The result is that the 

instructions must be executed in serial rather than 

parallel for a portion of the pipeline. A resource hazard 

is sometime referred to as a structural hazard. Let us 

consider a simple example of a resource 

hazard.Assume a simplified fivestage pipeline, in 

which each stage takes one clock cycle.

DATA HAZARDS:

         A dzata hazard occurs when there is a conflict in the access of an operand location. In 

general terms, we can state the haard in this form: Two instructions in a program are to 

be carried out sequentially and both make use of a specific register or memory operand.

If the 

two instructions are executed in strict sequence, no problem occurs. However,When instructions are carried out in a pipeline, the operand value may be

updated in such a way as to produce a different result than would occur with strict 

sequential execution. In other words, the program produces an incorrect result because 

of the use of pipelining. As an example, consider the following x86 machine instruction 

sequence:

                        ADD EAX, EBX /* EAX = EAX + EBX 

                    SUB ECX, EAX /* ECX = ECX - EAX

         The contents of the 32-bit registers EAX and EBX are added and stored in the first instruction. the result in EAX. In the second instruction, the contents of EAX are subtracted from ECX. Figure 12.16 shows the pipeline behavior. The ADD instruction 

does not update register EAX until the end of stage 5, which occurs at clock cycle 5. But 

the SUB instruction needs that value at the beginning of its stage 2, which occurs at clock 

cycle 4.To maintain correct operation, the pipeline must stall for two clocks cycles.Thus, 

Such a data hazard cannot be avoided without special hardware and avoidance algorithms.

results in inefficient pipeline usage. There are three types of data hazards;

TYPES OF DATA HAZARDS:

    • True dependency, or read after write (RAW),:  is An 

instruction modifies a register or memory location and a 

The data in that memory or the next instruction is read. register location: If the read occurs before, there is a risk.

    • Write after read (RAW), or antidependency: An 

instruction reads a register or memory location and a 

succeeding instruction writes to the location. A hazard occurs 

if the write operation completes before the read operation 

takes place. 

  • Write after write (RAW), or dependence on the output: TwO 

instructions both write  to the same location. A hazard occurs 

if the write operations take place in the reverse order of the 

intended sequence.

CONTROL HAZARDS

    A control hazard, also known as a 

branch hazard, occurs when the 

pipeline makes the wrong decision on a 

branch prediction and therefore brings 

instructions into the pipeline that must 

subsequently be discarded.We discuss 

approaches to dealing with control 

hazards next.

DEALING WITH BRANCHES

Dealing with conditional branches has been approached in a variety of ways:

      Multiple streams

      Prefetch branch target

      Loop buffer

      Branch prediction

      Delayed branch

MULTIPLE STREAMS:

A simple pipeline suffers a penalty for a branch instruction because 

It must choose between two fetching instructions and may choose the wrong option. Repetition is a brute-force strategy. the pipeline's initial sections and allow the pipeline to fetch,

both instructions, making use of two streams. There are two 

problems with this approach:

      When there are multiple pipelines, access delays are caused by contention.Additional branch instructions 

may enter the pipeline (either stream) before the original branch 

decision is resolved. Each such instruction needs an additional 

stream. Despite these drawbacks, this strategy can improve 

performance. performance.  Machines with two or more pipelines are examples.

streams are the IBM 370/168 and the IBM 3033.

PREFETCH BRANCH TARGET:

  When a conditional branch is recognized, the 

target of the branch is prefetched, in addition to 

the instruction following the branch.This target is 

then saved until the branch instruction is 

executed. If the branch is taken,the target has 

already been prefetched.The IBM 360/91 uses this 

approach.

LOOP BUFFER:

  A loop buffer is a small, fast memory that is managed by instruction fetch stage of the pipeline with the n latest retrieved directions, in that order. The hardware first determines whether a branch should be taken. Within the buffer is the branch target. If that's the case, the next instruction is retrieved from

buffer.The loop buffer has three benefits:

      1. The loop buffer will contain some instructions if prefetching is used. sequentially Prior to the fetch address of the current instruction. As a result, directions fetched sequentially will be accessible without incurring the usual memory access delay. 12.4 / PIPELINING INSTRUCTIONS 455 2.  If a branch reaches a single target, a few places before the address of the branch directions , the target will 

already be in the buffer.This is useful for the rather common occurrence of IF–

THEN and IF–THEN–ELSE sequences.

      3. This strategy is particularly well suited to dealing with loops, or iterations; 

hence the name loop buffer. If the loop buffer is sufficiently large to hold all instructions that are repeated in a loop, those instructions must be retrieved from memory..

only once, for the first iteration. For subsequent iterations, all the needed 

instructions are already in the buffer.The loop buffer is similar in principle to a 

cache dedicated to instructions.

The loop buffer, on the other hand, only stores instructions. in order and has a much smaller size, making it lower in

cost. Figure 12.17 gives an example of a loop buffer. If the 

buffer contains 256 bytes,

  Using byte addressing, the eight bits with the lowest significance are used.

are used to index the The remaining most significant bits are 

checked to see if the branch target is a part of the environment that the buffer has taken in. One of the machines Some of the CDC machines, like the Star-100, use a loop buffer. 6600, 7600), as well as the CRAY-1 A particular kind of loop

buffer is available on the Motorola 68010, for executing a 

three-instruction loop involving the DBcc (decrement and 

branch on condition) instruction (see Problem 12.14).A three 

word buffer is maintained, and these are carried out by the processor,

instructions  repeatedly until the loop condition is satisfied.